Chaitra: Email & Phone Number

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SoC Design Verification Engineer at Intel|Karnataka, India

Position:

SoC Design Verification Engineer at Intel

Location:

Karnataka, India

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Last updated: 2026-05-20

Updated: 2026-05-20

Found email addresses for Chaitra:

Business emails:

c*****a@intel.com

Personal emails:

c*********4@gmail.com

Found phone for Chaitra:

+91-***-***-3053

A different Chaitra?

Work Experience 2 years

SoC Design Verification Engineer at Intel

Aug 2025 - Current

Firmware Intern at Intel

Jul 2024 - Jul 2025

Chaitra started working in 2024, then the employee has changed 1 job. On average, Chaitra works for one company for 11 months.

Their professional focus is ARM Architecture, C (Programming Language), and C++ across 3 core areas.

Chaitra holds Introduction to Programming Using Python, 4.0 Tech Bootcamp, and Certificate of Internship certifications.

Education

Master of Technology - MTech at RV College Of Engineering

Bachelor of Engineering - BE at P D A College of Engineering, GULBARGA

Frequently Asked Questions

What is Chaitra's email address?

SignalHire found verified email addresses for Chaitra, both business and personal. Their business email is c*****a@intel.com, and personal emails include c*********4@gmail.com.

What is Chaitra's phone number?

SignalHire found a verified phone number for Chaitra: +91-***-***-3053.

How do I contact Chaitra at Intel?

You can reach Chaitra through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is Chaitra's professional background?

Chaitra has 2 years of professional experience. They have held roles including Firmware Intern at companies such as Intel. Their education includes Master of Technology - MTech from RV College Of Engineering, and Bachelor of Engineering - BE from P D A College of Engineering, GULBARGA.

Is Chaitra's contact information up to date?

Yes. Chaitra's SignalHire profile was last updated on 20 May 2026, reflecting their current position as SoC Design Verification Engineer at Intel in Santa Clara, California, United States.