YP Chen

YP Chen: Email & Phone Number

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FPGA ASIC Verification Architect at Intel|San Jose, California, United States

Position:

FPGA ASIC Verification Architect at Intel

Location:

San Jose, California, United States

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Last updated: 2024-10-13
Updated: 2024-10-13

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Education

MS at University of Michigan College of Engineering

Bachelor of Science - BS at National Cheng Kung University

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