Virendra Bind

Virendra Bind's email & phone

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Analog Design Engineer at Intel|Jaunpur, Uttar Pradesh, India

Position:

Analog Design Engineer at Intel

Location:

Jaunpur, Uttar Pradesh, India

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Last updated: 2026-04-26
Updated: 2026-04-26

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Work Experience 4 years

Analog Design Engineer at Intel

May 2025 - Current

Graduate Technical Intern at Intel

Jun 2024 - Apr 2025

Teaching Assistant at Indian Institute of Technology, Mandi

Aug 2023 - Jun 2024

Summer Intern at Banaras locomotive work (BLW) Varanasi

Jul 2022 - Aug 2022

Virendra Bind started working in 2022, then the employee has changed 2 companies and 3 jobs. On average, Virendra Bind works for one company for 8 months.

Education

Master of Technology - MTech VLSI at Indian Institute of Technology, Mandi

Bachelor of Technology - BTech at Kamla Nehru Institute of Technology, Sultanpur

Frequently Asked Questions

What is Virendra Bind's email address?

SignalHire found a verified business email address for Virendra Bind: b**********a@intel.com.

What is Virendra Bind's phone number?

SignalHire found a verified phone number for Virendra Bind: +91-***-***-2297.

How do I contact Virendra Bind at Intel?

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What is Virendra Bind's professional background?

Virendra Bind has 4 years of professional experience. They have held roles including Graduate Technical Intern, Teaching Assistant, and Summer Intern at companies such as Intel, Indian Institute of Technology, Mandi, and Banaras locomotive work (BLW) Varanasi. Their education includes Master of Technology - MTech VLSI from Indian Institute of Technology, Mandi, and Bachelor of Technology - BTech from Kamla Nehru Institute of Technology, Sultanpur.

Is Virendra Bind's contact information up to date?

Yes. Virendra Bind's SignalHire profile was last updated on 26 April 2026, reflecting their current position as Analog Design Engineer at Intel in Santa Clara, California, United States.

Virendra Bind Namesakes

Name
Company
Position
Virendra Bind
Adiraj Construction Company
Site Engineer

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