Virendra Bind

Virendra Bind: Email & Phone Number

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Analog Design Engineer at Intel|Jaunpur, Uttar Pradesh, India

Position:

Analog Design Engineer at Intel

Location:

Jaunpur, Uttar Pradesh, India

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Last updated: 2026-05-26
Updated: 2026-05-26

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Work Experience 4 years

Analog Design Engineer at Intel

May 2025 - Current

Graduate Technical Intern at Intel

Jun 2024 - Apr 2025

Teaching Assistant at Indian Institute of Technology, Mandi

Aug 2023 - Jun 2024

Summer Intern at Banaras locomotive work (BLW) Varanasi

Jul 2022 - Aug 2022

Virendra Bind started working in 2022, then the employee has changed 2 companies and 3 jobs. On average, Virendra Bind works for one company for 9 months.

Their professional focus is Amplifiers, Analog IC design, and Bandgap References across 3 core areas.

Virendra holds Non Conventional Energy Resources (NPTEL), Solar Energy Engineering and Technology (NPTEL), and Programming Fundamentals certifications.

Education

Master of Technology - MTech VLSI at Indian Institute of Technology, Mandi

Bachelor of Technology - BTech at Kamla Nehru Institute of Technology, Sultanpur

Virendra Bind Namesakes

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Virendra Bind
Adiraj Construction Company
Site Engineer
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