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Apr 2026 - Current
Sep 2025 - Apr 2026
Santhosh is proficient in English, Hindi, and Tamil. Their professional focus is Formal Verification, SystemVerilog, and Universal Verification Methodology (UVM) across 3 core areas.
Santhosh holds VLSI Design Flow : RTL to GDS, VLSI for Beginners, and SOC Design using Verilog HDL certifications.
Education
Bachelor of Engineering - BE at Kumaraguru College of Technology
Grade 12 at Maharishi Vidya Mandir Senior Secondary School
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