Peter

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Senior Engineering Manager SoC Memory & Cache Systems at Intel|Santa Clara, California, United States

Position:

Senior Engineering Manager SoC Memory & Cache Systems at Intel

Location:

Santa Clara, California, United States

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Last updated: 2026-07-03
Updated: 2026-07-03

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Work Experience 23 years

Senior Engineering Manager SoC Memory & Cache Systems at Intel

Oct 2021 - Current

Engineering Manager Memory Systems at Intel

Jun 2019 - Sep 2021

Senior IC Design Engineer SRAM Circuit Design at Arm

Oct 2013 - May 2018

Senior SoC Design Engineer Memory IP at Arm

Jul 2009 - Sep 2013

SoC Design Engineer SRAM and Cache Systems at Arm

Jun 2006 - Jun 2009

R&D Engineer Electronic Design Automation & Library Development at Synopsys Inc

Apr 2003 - May 2006

Peter started working in 2003, then the employee has changed 2 companies and 5 jobs. On average, Peter works for one company for 3 years 8 months.

Their professional focus is 7nm Semiconductor Design Coordination, 65nm / Deep Submicron Design, and 90nm / 130nm Process Technology across 3 core areas.

Education

Master of Science Electrical Engineering at University of California, Santa Cruz

Skills

90nm / 130nm Process Technology, 65nm / Deep Submicron Design, 7nm Semiconductor Design Coordination

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