Peter Chen: Email & Phone Number

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Silicon Design Engineer 2 at AMD|Toronto, Ontario, Canada

Position:

Silicon Design Engineer 2 at AMD

Location:

Toronto, Ontario, Canada

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Last updated: 2026-04-21

Updated: 2026-04-21

Found email addresses for Peter Chen:

Business emails:

c**n@amd.com

Personal emails:

p***@aol.com,

c***@gmail.com,

c***@groq.com,

p***@yahoo.ca

Found phones for Peter Chen:

+1-306-***-**62,

+1-902-***-**50,

+1-604-***-**29,

+1-306-***-**30

A different Peter Chen?

Work Experience 4 years

Silicon Design Engineer 2 at AMD

Sep 2025 - Current

ASIC Design Intern at Groq

Sep 2022 - Aug 2023

Peter Chen started working in 2022, then the employee has changed 1 company and 1 job. On average, Peter Chen works for one company for 10 months.

Their professional focus is Application-Specific Integrated Circuits (ASIC), C (Programming Language), and C++ across 3 core areas.

Education

Bachelor of Applied Science - BASc at University of Toronto

Frequently Asked Questions

What is Peter Chen's email address?

SignalHire found verified email addresses for Peter Chen, both business and personal. Their business email is c**n@amd.com, and personal emails include p***@aol.com, c***@gmail.com, and c***@groq.com.

What is Peter Chen's phone number?

SignalHire found multiple verified phone numbers for Peter Chen: +1-306-***-**62, +1-902-***-**50, and +1-604-***-**29.

How do I contact Peter Chen at AMD?

You can reach Peter Chen through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is Peter Chen's professional background?

Peter Chen has 4 years of professional experience. They have held roles including ASIC Design Intern at companies such as Groq. Their education includes Bachelor of Applied Science - BASc from University of Toronto.

Is Peter Chen's contact information up to date?

Yes. Peter Chen's SignalHire profile was last updated on 21 April 2026, reflecting their current position as Silicon Design Engineer 2 at AMD in Santa Clara, California, United States.