
Position:
IC Layout at Analog Bits
Location:
San Jose, California, United States
Found email addresses for Mark:
Found phones for Mark:
Prospect analytics
Apr 2024 - Current
Nov 2022 - May 2023
Their professional focus is Application-Specific Integrated Circuits (ASIC), Cadence Schematic Capture, and Cadence Virtuoso Layout Editor across 3 core areas.
Associate's degree at Los Angeles Valley College
Certificated at Silicon Drafting institute
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