Haiming Yu

Haiming Yu: Email & Phone Number

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Principal Engineer Memory and Testing at Intel|San Jose, California, United States

Position:

Principal Engineer Memory and Testing at Intel

Location:

San Jose, California, United States

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Last updated: 2024-04-12
Updated: 2024-04-12

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Work Experience 29 years

Principal Engineer Memory and Testing at Intel

Jun 2017 - Current

Product Engineer at Intel

Dec 2015 - Jun 2017

Principal Product Engineer at Altera

Jun 2012 - Dec 2015

Manager, IC Engineering at Altera

Jun 2001 - Jun 2012

Senior Design Engineer at HAL Computer Systems

Jun 1999 - Jun 2001

Design Engineer at Broadcom

Jun 1997 - Jun 1999

Haiming Yu started working in 1997, then the employee has changed 3 companies and 5 jobs. On average, Haiming Yu works for one company for 4 years 10 months.

Their professional focus is Analog Circuit Design, ASIC, and CMOS across 3 core areas.

Education

Ph.D. at University of Washington

Ph.D. Candidate at New Jersey Institute of Technology

M.S. at Southeast University

B.S. at Fudan University

Haiming Yu Namesakes

Name
Company
Position
Haiming Yu
Zhejiang University of Science and Technology
Lecturer
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