Chris Vuong

Chris Vuong: Email & Phone Number

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Incoming ASIC Physical Design Engineer Intern at Cisco|San Francisco Bay Area, United States

Position:

Incoming ASIC Physical Design Engineer Intern at Cisco

Location:

San Francisco Bay Area, United States

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Last updated: 2026-05-24
Updated: 2026-05-24

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Work Experience 3 years

Incoming ASIC Physical Design Engineer Intern at Cisco

Aug 2026 - Current

FPGA Design Engineer Intern at Lockheed Martin

May 2026 - Current

Undergraduate Researcher at PSyLab @ Georgia Tech

Apr 2026 - Current

Researcher (Computational Astrophysics) at UC Irvine

Jun 2023 - Aug 2023

Chris Vuong started working in 2023, then the employee has changed 3 companies and 3 jobs. On average, Chris Vuong works for one company for 2 months.

Chris is proficient in English and Vietnamese.

Education

Bachelor of Science at Georgia Institute of Technology

Frequently Asked Questions

What is Chris Vuong's email address?

SignalHire found verified email addresses for Chris Vuong, both business and personal. Their business email is v**@cisco.com, and personal emails include c********g@gatech.edu.

What is Chris Vuong's phone number?

SignalHire found a verified phone number for Chris Vuong: +1-***-***-7167.

How do I contact Chris Vuong at Cisco?

You can reach Chris Vuong through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is Chris Vuong's professional background?

Chris Vuong has 3 years of professional experience. They have held roles including FPGA Design Engineer Intern, Undergraduate Researcher, and Researcher (Computational Astrophysics) at companies such as Lockheed Martin, PSyLab @ Georgia Tech, and UC Irvine. Their education includes Bachelor of Science from Georgia Institute of Technology.

Is Chris Vuong's contact information up to date?

Yes. Chris Vuong's SignalHire profile was last updated on 24 May 2026, reflecting their current position as Incoming ASIC Physical Design Engineer Intern at Cisco in San Jose, CA, United States.

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