Position:
Intern at VLSI System Design
Location:
Chennai, Tamil Nadu, India
Found email addresses for Aashish Niranjan:
Found phone for Aashish Niranjan:
Dec 2025 - Current
May 2026 - Jul 2026
Mar 2026 - Apr 2026
Jan 2026 - Mar 2026
Dec 2025 - Jan 2026
Dec 2025 - Jan 2026
Dec 2024 - Jan 2026
Aug 2025 - Sep 2025
Jan 2025 - Mar 2025
Dec 2024 - Dec 2024
Sep 2024 - Oct 2024
Aashish is proficient in English, Hindi, and Japanese. Their professional focus is Advanced Data Analysis, Agentic AI Development, and Analog Circuit Design across 3 core areas.
Aashish holds Embedded Systems Workshop, VLSI Digital Design - Chip Design and Verilog Programming, and RISC-V Hackthon certifications and has been awarded 2nd Place – Paper Presentation SLICe ’26, 2nd Place – IEEE International Test Conference (ITC India) 2026 Hackathon, and Certificate of Appreciation – Paper Presentation (NCET-2025)
Bachelor of Technology - BTech at SRM IST Vadapalani Campus
High School at Kendriya Vidyalaya (KV)
SRM Institute of Science and Technology (SRMIST)
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