Riteshkumar Patil

Riteshkumar Patil: Email & Phone Number

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Analog Layout Design Trainee at Takshila Institute of VLSI Technologies|Pune, Maharashtra, India

Position:

Analog Layout Design Trainee at Takshila Institute of VLSI Technologies

Location:

Pune, Maharashtra, India

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Last updated: 2026-02-14
Updated: 2026-02-14

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Work Experience 2 years

Analog Layout Design Trainee at Takshila Institute of VLSI Technologies

Sep 2025 - Current

Research And Development Intern at SuryaLogix

Jun 2024 - Dec 2024

Riteshkumar Patil started working in 2024, then the employee has changed 1 company and 1 job. On average, Riteshkumar Patil works for one company for 9 months.

Their professional focus is Arduino, Cadence Virtuoso, and CMOS across 3 core areas.

Education

Bachelor of Technology - BTech at Vishwakarma Institute of Information Technology

HSC at TES'S BHUSAWAL ARTS,SCIENCE & P.O.NAHATA COMMERCE COLLEGE, BHUSAWAL.

Tapti Public School

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