Lin: Email & Phone Number

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Senior Design Engineer---FPGA User Interface IP at Intel|Santa Clara, California, United States

Position:

Senior Design Engineer---FPGA User Interface IP at Intel

Location:

Santa Clara, California, United States

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Last updated: 2026-07-21

Updated: 2026-07-21

Found email addresses for Lin:

Business emails:

l**@intel.com

Personal emails:

l***@yahoo.com,

l***@lg.com,

l***@skhms.com,

l***@aol.com

Found phones for Lin:

+1-323-***-**68,

+1-909-***-**54

A different Lin?

Work Experience 11 years

Senior Design Engineer---FPGA User Interface IP at Intel

Jun 2018 - Current

Senior SoC Design Engineer at SK hynix memory solutions America Inc.

Dec 2015 - Jun 2018

Research Engineer at LG Electronics

Jan 2015 - Nov 2015

Lin started working in 2015, then the employee has changed 2 companies and 2 jobs. On average, Lin works for one company for 3 years 10 months.

Their professional focus is ASIC Design and Verification, C, and matlab across 3 core areas.

Education

Master of Science - MS at University of Southern California

Master of Science - MS at San Jose State University

Frequently Asked Questions

What is Lin's email address?

SignalHire found verified email addresses for Lin, both business and personal. Their business email is l**@intel.com, and personal emails include l***@yahoo.com, l***@lg.com, and l***@skhms.com.

What is Lin's phone number?

SignalHire found multiple verified phone numbers for Lin: +1-323-***-**68, and +1-909-***-**54.

How do I contact Lin at Intel?

You can reach Lin through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is Lin's professional background?

Lin has 11 years of professional experience. They have held roles including Senior SoC Design Engineer, and Research Engineer at companies such as SK hynix memory solutions America Inc., and LG Electronics. Their education includes Master of Science - MS from University of Southern California, and Master of Science - MS from San Jose State University.

Is Lin's contact information up to date?

Yes. Lin's SignalHire profile was last updated on 21 July 2026, reflecting their current position as Senior Design Engineer---FPGA User Interface IP at Intel in Santa Clara, California, United States.

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LIN

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Lin

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