Jayashiny Devadhas: Email & Phone Number

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Soc Design Verification Engineer at Intel|Greater Bengaluru Area, India

Position:

Soc Design Verification Engineer at Intel

Location:

Greater Bengaluru Area, India

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Last updated: 2026-07-23

Updated: 2026-07-23

Found email addresses for Jayashiny Devadhas:

Business emails:

d***************y@intel.com

Found phone for Jayashiny Devadhas:

+91-***-***-2494

A different Jayashiny Devadhas?

Work Experience 8 years

Soc Design Verification Engineer at Intel

May 2019 - Current

Modem Verification Engineer at Intel

May 2018 - Apr 2019

Jayashiny Devadhas started working in 2018, then the employee has changed 1 job. On average, Jayashiny Devadhas works for one company for 4 years 1 month.

Jayashiny is proficient in English, Malayalam, and Tamil. Their professional focus is 3GPP Spec - LTE 5G, BFM Integration, and Co-Simulation across 3 core areas.

Education

Bachelor of Engineering - BE at Government College of Engineering, Tirunelveli

Frequently Asked Questions

What is Jayashiny Devadhas's email address?

SignalHire found a verified business email address for Jayashiny Devadhas: d***************y@intel.com.

What is Jayashiny Devadhas's phone number?

SignalHire found a verified phone number for Jayashiny Devadhas: +91-***-***-2494.

How do I contact Jayashiny Devadhas at Intel?

You can reach Jayashiny Devadhas through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is Jayashiny Devadhas's professional background?

Jayashiny Devadhas has 8 years of professional experience. They have held roles including Modem Verification Engineer at companies such as Intel. Their education includes Bachelor of Engineering - BE from Government College of Engineering, Tirunelveli.

Is Jayashiny Devadhas's contact information up to date?

Yes. Jayashiny Devadhas's SignalHire profile was last updated on 23 July 2026, reflecting their current position as Soc Design Verification Engineer at Intel in Santa Clara, California, United States.

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