Position:
Incoming DFT & DV Engineer Intern at NXP Semiconductors
Location:
United States
Found email addresses for Jason:
Found phone for Jason:
Apr 2026 - Current
Aug 2025 - Apr 2026
Jul 2025 - Aug 2025
May 2025 - May 2025
Their professional focus is Circuit Design, Cleanroom Process, and Cleanroom Protocols across 3 core areas.
Jason holds FPGA Design, Logic Circuit Design, and Semiconductor Fabrication certifications and has been awarded 1st Place in Summer Internship, Dean’s List (2025), and Dean’s List (2024)
Bachelor of Science - BS at Purdue University College of Engineering
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