Gerry Toll

Gerry Toll: Email & Phone Number

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Principal Engineer, CPU Microcode Architecture at Intel|Portland, Oregon, United States

Position:

Principal Engineer, CPU Microcode Architecture at Intel

Location:

Portland, Oregon, United States

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Last updated: 2026-05-03
Updated: 2026-05-03

Found email addresses for Gerry Toll:

Business emails:
Personal emails:
g***@gmail.com,
g***@aol.com,
g***@yahoo.com

Found phones for Gerry Toll:

+1-623-***-**38
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Work Experience 29 years

Principal Engineer, CPU Microcode Architecture at Intel

Jul 2021 - Current

Security Architect, Data Center Group at Intel

Nov 2018 - Jul 2021

Senior Design Engineer, CPU Microcode at Intel

Jan 2003 - Nov 2018

Validation Engineer, Multiprocessing and Memory Coherence at Intel

Aug 1997 - Jan 2003

Gerry Toll started working in 1997, then the employee has changed 3 jobs. On average, Gerry Toll works for one company for 7 years 3 months.

Their professional focus is C, Cache Coherency, and Computer Architecture across 3 core areas.

Education

Cornell University

Frequently Asked Questions

What is Gerry Toll's email address?

SignalHire found verified email addresses for Gerry Toll, both business and personal. Their business email is t*******y@intel.com, and personal emails include t***@intel.com, g***@gmail.com, and g***@aol.com.

What is Gerry Toll's phone number?

SignalHire found multiple verified phone numbers for Gerry Toll: +1-909-***-**28, and +1-623-***-**38.

How do I contact Gerry Toll at Intel?

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What is Gerry Toll's professional background?

Gerry Toll has 29 years of professional experience. They have held roles including Security Architect, Data Center Group, Senior Design Engineer, CPU Microcode, and Validation Engineer, Multiprocessing and Memory Coherence at companies such as Intel, Intel, and Intel. Their education includes Cornell University.

Is Gerry Toll's contact information up to date?

Yes. Gerry Toll's SignalHire profile was last updated on 3 May 2026, reflecting their current position as Principal Engineer, CPU Microcode Architecture at Intel in Santa Clara, California, United States.

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