George Chen: Email & Phone Number

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Principal FPGA Design Engineer at Lattice Semiconductor|San Jose, California, United States

Position:

Principal FPGA Design Engineer at Lattice Semiconductor

Location:

San Jose, California, United States

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Last updated: 2026-05-15

Updated: 2026-05-15

Found email addresses for George Chen:

Business emails:

g**********n@amd.com

Personal emails:

g***@intel.com,

c***@aol.com,

c***@rapidsilicon.com,

c***@gmail.com

Found phones for George Chen:

+1-323-***-**29,

+1-623-***-**13,

+1-870-***-**47,

+1-323-***-**96

A different George Chen?

Work Experience 31 years

Principal FPGA Design Engineer at Lattice Semiconductor

Jun 2026 - Current

Principal Engineer, SOC Logic Design at Altera

Mar 2024 - Jun 2026

Senior Principal Engineer, Hardware Modeling at Rapid Silicon

May 2023 - Mar 2024

SOC Design Engineer at Intel

Dec 2015 - May 2023

Principal Engineer at Altera

Sep 2014 - Dec 2015

Senior Member of Technical Staff at Altera

Apr 2012 - Sep 2014

Senior Principal Hardware Engineer at Oracle

Apr 2011 - Apr 2012

Principal Hardware Engineer at Oracle

Jan 2010 - Apr 2011

Senior Staff Engineer at Sun Microsystems

Feb 2000 - Feb 2010

Senior Staff Engineer at Cirrus Logic

Dec 1998 - Feb 2000

CAD Manager at Weltrend Semiconductors

Jul 1997 - Sep 1998

Electronics Team Manager at Victory Industrial Corporation

Jan 1995 - Jan 1997

George Chen started working in 1995, then the employee has changed 8 companies and 10 jobs. On average, George Chen works for one company for 2 years 7 months.

George is proficient in Chinese and English. Their professional focus is 68hc908, Application-Specific Integrated Circuits (ASIC), and ASIC across 3 core areas.

George holds Python: Decorators certifications and has registered patents, including "Method of analyzing interconnect for global circuit wires, Highly Threaded Static Timer, and Multithreaded Static Timing Analysis".

Education

Bachelor of Science (BS) at Caltech

Doctor of Philosophy (PhD) at Stanford University

Master of Science (MS) at Stanford University

Frequently Asked Questions

What is George Chen's email address?

SignalHire found verified email addresses for George Chen, both business and personal. Their business email is g**********n@amd.com, and personal emails include g***@intel.com, c***@aol.com, and c***@rapidsilicon.com.

What is George Chen's phone number?

SignalHire found multiple verified phone numbers for George Chen: +1-323-***-**29, +1-623-***-**13, and +1-870-***-**47.

How do I contact George Chen at Lattice Semiconductor?

You can reach George Chen through SignalHire by unlocking their verified email and direct phone number (free signup, no credit card needed). SignalHire is the fastest route if you need their contact details immediately.

What is George Chen's professional background?

George Chen has 31 years of professional experience. They have held roles including Principal Engineer, SOC Logic Design, Senior Principal Engineer, Hardware Modeling, and SOC Design Engineer at companies such as Altera, Rapid Silicon, and Intel. Their education includes Bachelor of Science (BS) from Caltech, and Doctor of Philosophy (PhD) from Stanford University.

Is George Chen's contact information up to date?

Yes. George Chen's SignalHire profile was last updated on 15 May 2026, reflecting their current position as Principal FPGA Design Engineer at Lattice Semiconductor in Hillsboro, Oregon, United States.

George Chen Namesakes

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George Chen

Zebra Technologies

Director of UX Research and Innovation

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George

St. John's University

University Student

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George Chen

Point72

Analyst

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Other employees at Lattice Semiconductor

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Position

Sai Kiran Gundeti

Altera

Graduate Trainee

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Srivarsha Bathula

Altera

FPGA Solutions Validation Engineer

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Ajay Babu

Altera

Data Engineer

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Tom Wang

Altera

FPGA IP Engineer

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Ilan Truanovsky

Altera

Software Engineer

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Nikita Bogatyrev

Altera

Software Engineer

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sm ihm

Altera

pharma

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Venkata Sai Pranav Twarakavi

Altera

SoC Design Verification Engineer

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Justin Lo

Altera

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Nor Aqilah Amira Badrul Hisham

Altera

SoC Physical Design Engineer

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