Bee Lay Cheah

Bee Lay Cheah: Email & Phone Number

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Fullchip Power Convergence Owner | SoC Datamining | Physical Design Engineer at Intel|Bayan Lepas, Penang, Malaysia

Position:

Fullchip Power Convergence Owner | SoC Datamining | Physical Design Engineer at Intel

Location:

Bayan Lepas, Penang, Malaysia

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Last updated: 2026-05-05
Updated: 2026-05-05

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Work Experience 19 years

Fullchip Power Convergence Owner | SoC Datamining | Physical Design Engineer at Intel

May 2024 - Current

Technical Staff Design Engineer at Microchip Technology Inc.

Jun 2023 - May 2024

Staff Design Engineer at Intel

Jun 2007 - Jun 2023

Bee Lay Cheah started working in 2007, then the employee has changed 1 company and 2 jobs. On average, Bee Lay Cheah works for one company for 6 years 4 months.

Their professional focus is Analytical Skills, ASIC, and Data Analysis across 3 core areas.

Education

Bachelor of Electrical Engineering at Universiti Teknologi Malaysia

Skills

Semiconductors, Synopsys tools, Microsoft Outlook, Primetime, Verilog, Low-power Design, Microsoft Excel, Perl, Debugging, SoC, Functional Verification, ASIC, Microprocessors, High Speed Design, Static Timing Analysis, TCL, Physical Design, Synopsys Primetime, Power Optimization, Analytical Skills, Data Analysis, VLSI

Frequently Asked Questions

What is Bee Lay Cheah's email address?

SignalHire found a verified business email address for Bee Lay Cheah: l****e@intel.com.

What is Bee Lay Cheah's phone number?

SignalHire found a verified phone number for Bee Lay Cheah: +60-***-***-7002.

How do I contact Bee Lay Cheah at Intel?

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What is Bee Lay Cheah's professional background?

Bee Lay Cheah has 19 years of professional experience. They have held roles including Technical Staff Design Engineer, and Staff Design Engineer at companies such as Microchip Technology Inc., and Intel. Their education includes Bachelor of Electrical Engineering from Universiti Teknologi Malaysia.

Is Bee Lay Cheah's contact information up to date?

Yes. Bee Lay Cheah's SignalHire profile was last updated on 5 May 2026, reflecting their current position as Fullchip Power Convergence Owner | SoC Datamining | Physical Design Engineer at Intel in Santa Clara, California, United States.

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